Fully Custom Astronomical Camera using the PiXi 2.0
This is the project that led to the development of the PiXi add-on for the Raspberry Pi in the first place. It’s a programmable slow-scan CCD camera readout controller & data acquisition system designed specifically for astro-photography.
The original project from 1993 used a Hitachi 8-bit processor card running a Forth interpreter. I think it ran at 4MHz and no, I’ve not missed any zeros off that figure.
Ok it was slow, especially since most of the code was running through the interpreter but it did the job at the time. In a way, it was probably a ‘90’s equivalent of the Raspberry Pi.
The CPU was not fast enough or accurate enough timing-wise to directly control the readout from the CCD. This task was done by a specially designed digital ‘sequencer’ that produced the precisely timed control signals needed to control the readout from the CCD and control the ADC and analogue signal processing needed to obtain a low-noise image signal from the CCD. After running through several variations of discrete logic based digital sequencers the final scheme did in fact use an FPGA. This was a 2,000 gate one-time programmable Actel ACT1020 which actually did the job very well. But the processor was still somewhat slow. So the plan was to upgrade the project using the processing power of the Raspberry Pi and the digital processing & I/O capabilities of a much more advanced 200,000 gate Xilinx FPGA. The following project concept goes some way to describe how it would be possible to use the PiXi to upgrade the project and bring a 20 year old camera project back to life…
Summary of PiXi functions that make this project possible:
GPIO1 (24 x 3.3v digital I/O):
11 x I/O used to control the 16-bit ADC and control the correlated double sampling background noise reduction & data interface;
13 x I/O spare (not used);
GPIO2 (16 x open-collector / open-drain outputs):
8 spare high-current output (not used);
8 spare low-current outputs (not used);
One possible future use for the high-current open-drain outputs is a control for a mechanical shutter mechanism.
The low-current open-collector outputs could be used to control an auto-guider port on a telescope.
GPIO3 (16 x 5v I/O):
6 x I/O used as the 4-phase vertical transfer clock controls & 2-phase readout controls on the CCD;
2 x I/O used as the 2-phase horizontal transfer clock controls on the CCD;
1 x I/O used as the output amplifier pre-charge clock control on the CCD;
1 x I/O used as the substrate clock control on the CCD;
6 x I/O spare (not used);
1 x I2C port spare;
1 x ADC input used to sample the pixel data (if used in place of external 16-bit ADC);
1 x ADC input used to sample the temperature of the CCD;
1 x ADC input used to sample the external temperature;
1 x ADC input used to sample the -9V CCD power supply status;
1 x ADC input used to sample the +15V CCD power supply status;
3 x ADC input spare (not used);
1 x DAC output to trim the CCD -9V power supply;
1 x DAC output to trim the CCD 15V power supply;
1 x DAC output to control the peltier cooler drive current;
1 x DAC outputs spare (not used).
RS232 Serial Interface:
Could be used as a camera control port, possibly linked to a telescope computer for remote-control of the telescope or even an observatory control system.
Implements the programmable sequence controller that controls the readout of the CCD. The FPGA is re-programmable which means that the readout control sequence can be easily tweaked or even completely re-designed to optimise the readout sequence of the CCD or even allow it to be changed to use a completely different CCD.
The original project comprised three single Euro-card sized boards mounted in a frame which also included two multi-output power supply modules and the Forth interpreter based processor. There was also a separate power supply to supply a high current to the Peltier effect coolers that were used to lower the CCD operating temperature. All in all it was a little on the large side…
The plan was to shrink this down to one or two considerably smaller boards mounted within the camera head with the Raspberry Pi mounted on the outside of the camera head. The functions within the camera head, apart from the PiXi would include the CCD imager itself, low-noise power supplies, biasing & CCD drivers, CCD output amplifier correlated double sampling & 16 (or 24) bit ADC.
A draft schematic of a possible implementation of the PiXi as a CCD imager readout controller can be found here.
This is kind of work in progress but the project has taken a back burner to allow us to concentrate on the PiXi development.
If you have any thoughts or questions about this project or maybe want some advice on your own camera project, please feel free to get in contact with us.